1. Field of the Invention
The present invention relates to a phase detector capable of doubling the resolution compared to a conventional sampling circuit, in which a first sampling circuit samples an input waveform by an input clock of a specific period to produce a first sampled waveform, a second sampling circuit samples the input waveform by a clock having a reverse phase to the input clock to produce a second sampled waveform, and a third sampling circuit samples the second sampled waveform by the first sampled waveform as a sampling clock.
2. Description of the Related Art
In the PCM communication system, input signals to be transmitted are sampled so as to convert the input signals into pulse amplitude modulation waves.
FIG. 3 is a block diagram showing an example of a conventional sampling circuit for performing such a sampling. In the example shown in FIG. 3, a D-type flip-flop (hereinafter, referred to as FF) is used for a sampling circuit.
In FIG. 3, an input waveform 1 enters an input terminal D of a FF 4, and a clock 2 of a specific period enters a clock input terminal CK of the FF 4. Thereby, the input waveform 1 is sampled to produce a sampled waveform 3 at an output terminal Q of the FF 4.
However, in the conventional sampling circuit, to enhance the resolution of the sampled waveform 3 needs to use a higher clock frequency for the clock 2, and to achieve a half resolution needs to double the frequency of the clock 2.